Conventional pattern sequence controllers used in present logic test systems provide a control code for every pattern in a test pattern set. Due to the nature of test patterns, this control code is typically highly redundant, for example, a typical test pattern set is comprised almost entirely of sequential or "straight line" patterns. This means that the test pattern addresses are sequential. Limited pattern compression is sometimes achieved by using a pattern control code to repeat individual patterns or loop on groups of patterns. The use of a control code for every pattern, as provided in prior art testers, is very inefficient.